
NVIDIA Announces CUDA Rust with cuda-oxide (SIMT) and cutile-rs (Tile) for Compile-Time-Safe GPU Kernels
NVIDIA has announced CUDA Rust, a push to make Rust a first-class language for writing GPU kernels. Rust code could already launch CUDA kernels, but the kernel body usually had to be written elsewhere. CUDA Rust closes that gap with two NVlabs open-source projects: cuda-oxide for the SIMT model and cutile-rs for the newer Tile model. Both compile Rust kernels natively and use Rust’s ownership rules to reject aliasing bugs at compile time. Is it deployable? Partially. cutile-rs is publ
NVIDIA has announced CUDA Rust, which enables writing GPU kernels directly in Rust rather than requiring developers to write kernel code in other languages. The announcement includes two open-source projects: cuda-oxide for the SIMT programming model and cutile-rs for the newer Tile model, both of which use Rust's compiler to catch memory aliasing bugs before code runs. This matters because the broader AI infrastructure layer, including inference engines and drivers, is increasingly written in Rust, making GPU kernels the remaining exception. The Tile approach is partially deployable with cutile-rs already used in production systems, while cuda-oxide remains in early alpha and neither project is confirmed ready for production use.
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Google Unveils TPU 8i Max and TPU 8tx: A Dual-Chip TPU and a Confidential TPU
Google has added two new systems to its eighth-generation TPU lineup. TPU 8i Max targets massive context windows and rack density. TPU 8tx targets secure, confidential inference. Google TPU 8i Max is a dual-chip package built from 2 TPU 8i chips. Both arrive alongside TPU 8t and TPU 8i, announced in April. TL;DR Size: TPU 8i Max = 2 TPU 8i chips in 1 package. TPU 8tx = TPU 8t silicon plus 5th Gen AMD EPYC hosts. Runs on: Google Cloud TPU systems. Performance: 8i Max doubles TPU 8
Also reported by Data Center Knowledge

IBM Announces IBM Quantum Nighthawk r3: A New Processor to Support 10k Quantum Operations on 520 Programmable Qubits
IBM has announced IBM Quantum Nighthawk r3, its next superconducting quantum processor. It is designed to run 10,000 quantum operations accurately across 520 programmable qubits. In 2027, IBM plans to link 2 r3 chips into a single 1,040-qubit system. For developers, the announcement is speed. The current Nighthawk r2 already runs workloads up to 19x faster than IBM’s earlier processors. TL;DR Size: Nighthawk r3: 520 programmable qubits, 2,034 physical qubits, 10 l-couplers. Nightha

Why the data center you dread might never even be built
The data center boom is running into serious real-world obstacles, from widespread local opposition and permitting delays to a scramble for electricity. Before those challenges even come into play, though, there’s a more basic problem: A lot of the projects being announced may never get built in the first place. With billions of dollars in AI infrastructure […]

How backlash and red tape continue to slow data centers post-Blue Wave
The data center boom is running into serious real-world obstacles, from widespread local opposition and permitting delays to a scramble for electricity. Before those challenges even come into play, though, there’s a more basic problem: A lot of the projects being announced may never get built in the first place. With billions of dollars in AI infrastructure […]

AMD Launches Epyc SP7, Helion as AI Rack Demand Rises
AMD has begun shipping sixth-gen Epyc servers and is rolling out Helion AI racks, signaling a bigger push into enterprise and agentic AI infrastructure.

Google broadens its AI hardware portfolio with two new specialized chips
Google's new tensor processing units (TPUs) broaden its chip portfolio to more use cases: confidential model training and more memory capacity.