IBM Pushes AI Chip Design Forward with Sub-1 nm NanoStack

IBM has developed a new transistor architecture called NanoStack that stacks transistor structures in three dimensions, enabling roughly 100 billion transistors on a chip and potentially delivering up to 50 percent higher performance or 70 percent lower energy consumption compared to earlier technology. For data center operators managing massive AI clusters, the significance lies in achieving more computing power from the same power budget, which matters as facility power requirements grow into the hundreds of megawatts. The technology represents a shift in how the semiconductor industry approaches chip scaling beyond current nanosheet designs, though moving from research demonstration to actual manufacturing remains a significant challenge. IBM expects this technology to become mainstream across the semiconductor industry within a decade.