IBM Pushes AI Chip Design Forward with Sub-1 nm NanoStack
IBM’s NanoStack transistor platform promises to extend chip scaling beyond nanosheets, offering improvements in AI performance, memory density, and energy efficiency.
IBM has developed a new transistor architecture called NanoStack that stacks transistor structures in three dimensions, enabling roughly 100 billion transistors on a chip and potentially delivering up to 50 percent higher performance or 70 percent lower energy consumption compared to earlier technology. For data center operators managing massive AI clusters, the significance lies in achieving more computing power from the same power budget, which matters as facility power requirements grow into the hundreds of megawatts. The technology represents a shift in how the semiconductor industry approaches chip scaling beyond current nanosheet designs, though moving from research demonstration to actual manufacturing remains a significant challenge. IBM expects this technology to become mainstream across the semiconductor industry within a decade.
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Google Unveils TPU 8i Max and TPU 8tx: A Dual-Chip TPU and a Confidential TPU
Google has added two new systems to its eighth-generation TPU lineup. TPU 8i Max targets massive context windows and rack density. TPU 8tx targets secure, confidential inference. Google TPU 8i Max is a dual-chip package built from 2 TPU 8i chips. Both arrive alongside TPU 8t and TPU 8i, announced in April. TL;DR Size: TPU 8i Max = 2 TPU 8i chips in 1 package. TPU 8tx = TPU 8t silicon plus 5th Gen AMD EPYC hosts. Runs on: Google Cloud TPU systems. Performance: 8i Max doubles TPU 8
Also reported by Data Center Knowledge
IBM Announces IBM Quantum Nighthawk r3: A New Processor to Support 10k Quantum Operations on 520 Programmable Qubits
IBM has announced IBM Quantum Nighthawk r3, its next superconducting quantum processor. It is designed to run 10,000 quantum operations accurately across 520 programmable qubits. In 2027, IBM plans to link 2 r3 chips into a single 1,040-qubit system. For developers, the announcement is speed. The current Nighthawk r2 already runs workloads up to 19x faster than IBM’s earlier processors. TL;DR Size: Nighthawk r3: 520 programmable qubits, 2,034 physical qubits, 10 l-couplers. Nightha
Why the data center you dread might never even be built
The data center boom is running into serious real-world obstacles, from widespread local opposition and permitting delays to a scramble for electricity. Before those challenges even come into play, though, there’s a more basic problem: A lot of the projects being announced may never get built in the first place. With billions of dollars in AI infrastructure […]
How backlash and red tape continue to slow data centers post-Blue Wave
The data center boom is running into serious real-world obstacles, from widespread local opposition and permitting delays to a scramble for electricity. Before those challenges even come into play, though, there’s a more basic problem: A lot of the projects being announced may never get built in the first place. With billions of dollars in AI infrastructure […]
AMD Launches Epyc SP7, Helion as AI Rack Demand Rises
AMD has begun shipping sixth-gen Epyc servers and is rolling out Helion AI racks, signaling a bigger push into enterprise and agentic AI infrastructure.
Google broadens its AI hardware portfolio with two new specialized chips
Google's new tensor processing units (TPUs) broaden its chip portfolio to more use cases: confidential model training and more memory capacity.