Hardware & Compute

DFlash Speculative Decoding Drafts Whole Token Blocks in Parallel for Up to 15x Higher Throughput on NVIDIA Blackwell

Autoregressive large language models generate text one token at a time. Each token waits for the one before it. This serial loop leaves modern GPUs underused and keeps inference slow. The cost grows worse with long Chain-of-Thought reasoning models. Their lengthy outputs make latency the dominant part of generation. Speculative decoding is the standard fix. A small draft model proposes future tokens. The large target model verifies those tokens in parallel. Accepted tokens are kept, so the o

Get smart on it

Autoregressive language models generate text one token at a time, which leaves modern GPUs underused and slows inference. Speculative decoding addresses this by having a small draft model propose future tokens that a large target model verifies in parallel, but existing methods still draft tokens one at a time, limiting speedups to around 2-3x. DFlash introduces a block diffusion model that proposes entire blocks of tokens in a single forward pass rather than one at a time, with the target model verifying those blocks in parallel. Research reports over 6x lossless acceleration across various models and tasks, reaching up to 15x higher throughput on NVIDIA Blackwell hardware, with particular benefits for coding agents, reasoning models with long outputs, and high-throughput serving scenarios.

Explainer: Why AI Is Getting Faster Without Getting Smarter: Speculative Decoding Explained

The biggest AI stories, once a day

One short email a day with the stories that matter. Free. Unsubscribe with one click.

Relevant courses

Want to go deeper than the news? Explore live, cohort-based AI courses taught by practitioners.

Browse AI courses on Maven
Related news
Hardware & ComputeOpen story →

Google Unveils TPU 8i Max and TPU 8tx: A Dual-Chip TPU and a Confidential TPU

Google has added two new systems to its eighth-generation TPU lineup. TPU 8i Max targets massive context windows and rack density. TPU 8tx targets secure, confidential inference. Google TPU 8i Max is a dual-chip package built from 2 TPU 8i chips. Both arrive alongside TPU 8t and TPU 8i, announced in April. TL;DR Size: TPU 8i Max = 2 TPU 8i chips in 1 package. TPU 8tx = TPU 8t silicon plus 5th Gen AMD EPYC hosts. Runs on: Google Cloud TPU systems. Performance: 8i Max doubles TPU 8

Also reported by Data Center Knowledge

Hardware & ComputeOpen story →

IBM Announces IBM Quantum Nighthawk r3: A New Processor to Support 10k Quantum Operations on 520 Programmable Qubits

IBM has announced IBM Quantum Nighthawk r3, its next superconducting quantum processor. It is designed to run 10,000 quantum operations accurately across 520 programmable qubits. In 2027, IBM plans to link 2 r3 chips into a single 1,040-qubit system. For developers, the announcement is speed. The current Nighthawk r2 already runs workloads up to 19x faster than IBM’s earlier processors. TL;DR Size: Nighthawk r3: 520 programmable qubits, 2,034 physical qubits, 10 l-couplers. Nightha

Hardware & ComputeOpen story →

Why the data center you dread might never even be built

The data center boom is running into serious real-world obstacles, from widespread local opposition and permitting delays to a scramble for electricity. Before those challenges even come into play, though, there’s a more basic problem: A lot of the projects being announced may never get built in the first place. With billions of dollars in AI infrastructure […]

Hardware & ComputeOpen story →

How backlash and red tape continue to slow data centers post-Blue Wave

The data center boom is running into serious real-world obstacles, from widespread local opposition and permitting delays to a scramble for electricity. Before those challenges even come into play, though, there’s a more basic problem: A lot of the projects being announced may never get built in the first place. With billions of dollars in AI infrastructure […]

Hardware & ComputeOpen story →

AMD Launches Epyc SP7, Helion as AI Rack Demand Rises

AMD has begun shipping sixth-gen Epyc servers and is rolling out Helion AI racks, signaling a bigger push into enterprise and agentic AI infrastructure.

Hardware & ComputeOpen story →

Google broadens its AI hardware portfolio with two new specialized chips

Google's new tensor processing units (TPUs) broaden its chip portfolio to more use cases: confidential model training and more memory capacity.